Method and system for managing address bits during buffered program operations in a memory device
US7404049B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2005 |
| Grant date | Jul 22, 2008 |
| Priority date | — |
| Expiry date | Aug 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for managing a buffered program operation for plurality of words is described. In one aspect, the method and system include providing an internal buffer including a plurality of locations and at least one bit location for the plurality of locations. Each of the words is stored in a location of the plurality of locations. The words are associated with internal address bits for the locations. At least one of the internal address bits is at least one group address bit that corresponds to all of the words. A remaining portion of the internal address bits is associated at least one of the words. The at least one bit location stores the at least one group address bit for the words. Thus, in one aspect, the method and system include storing each of the words one of the buffer locations. The method and system also include associating the at least one group address bit with the buffer location for each of the words.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.