Method of operating a memory device, memory module, and a memory device comprising the memory module

US7404050B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventor

• Peter Gregorius · Munich, DE

Key dates

• Filing date: Aug 1, 2005
• Grant date: Jul 22, 2008
• Expiry date: May 14, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F13/4243
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

There is provided a method of operating a memory device comprising at least one memory module, a corresponding memory module and a memory device comprising the at least one memory module. It is proposed that in the memory module (100a, 100b, 100c, 100d) a command and write data signal (CA, WD) is received and a read data signal (RD) is transmitted from the memory module (100a, 100b, 100c, 100d). Further, an input clock signal (CLK) is received in the memory module (100a, 100b, 100c, 100d) and is regenerated by means of a clock synthesizer unit (150) of the memory module (100a, 100b, 100c, 100d) to produce a regenerated input clock signal of the memory module (100a, 100b, 100c, 100d). The read data signal (RD) transmitted from the memory module (100a, 100b, 100c, 100d) is synchronized to the regenerated input clock signal of the memory module (100a, 100b, 100c, 100d). For this purpose, the clock synthesizer unit (150) preferably comprises a phase-locked loop.