Electrically erasable programmable read-only memory cell and memory device
US7405442B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2006 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | Nov 22, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/683
Abstract
A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer and used as a control gate. Thereafter, a floating gate is formed over the inter-gate dielectric layer and the tunnel layer. Thereafter, a source region and a drain region are formed in the substrate beside two sides of the floating gate under the tunnel layer. Especially, the manufacturing method of the memory cell can be integrated with the manufacturing process of high operation voltage component and low operation voltage component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.