Delayed Locked Loop Circuit
US7405603B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 6, 2006 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | Dec 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Delayed Locked Loop Circuit of DLL comprises a buffer that receives a power-down signal and an inverted signal of a first clock signal; first and second delay lines an output device that outputs signals corresponding to the output signals of the first and second delay lines respectively; a replica delay unit, a phase comparator for comparing a phase difference between the output signal of the second buffer and the output signal of the replica delay unit; and a delay line controller for controlling delay times of the first delay line and the second delay line by corresponding to a comparison result of the phase comparator. The DLL circuit is configured such that the first and second buffers are disabled when the power-down mode entry notifying signal corresponding to a power-down mode is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.