Young-Jun Ku
52Patents
6h-index
26Co-inventors
68Inventor score
Filing activity: Dec 28, 2005 → Dec 2, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8441831B2 | Semiconductor integrated circuit having stacked semiconductor chips and vias therebetween | Electricity | 17 | Active |
| US8339879B2 | Repair circuit and semiconductor apparatus including the same | Electricity | 10 | Active |
| US7994834B2 | Duty cycle corrector and clock generator having the same | Electricity | 10 | Active |
| US7639552B2 | Delay locked loop and semiconductor memory device with the same | Physics | 10 | Active |
| US7676686B2 | Delay locked loop circuit and synchronous memory device including the same | Electricity | 8 | Active |
| US7777542B2 | Delay locked loop | Electricity | 6 | Active |
| US7489170B2 | Delay locked loop in synchronous semiconductor memory device and driving method thereof | Electricity | 6 | Active |
| US7940096B2 | Register controlled delay locked loop circuit | Electricity | 5 | Active |
| US7706199B2 | Circuit and method for parallel test of memory device | Physics | 5 | Active |
| US8373478B2 | Semiconductor device and delay locked loop circuit thereof | Electricity | 5 | Active |
| US7405603B2 | Delayed Locked Loop Circuit | Electricity | 4 | Active |
| US7545189B2 | Delayed locked loop circuit | Electricity | 4 | Active |
| US7450439B2 | Apparatus for generating internal voltage | Physics | 4 | Active |
| US7872508B2 | Delay locked loop circuit | Electricity | 3 | Active |
| US7492653B2 | Semiconductor memory device capable of effectively testing failure of data | Physics | 3 | Active |
| US8411478B2 | Three-dimensional stacked semiconductor integrated circuit | Electricity | 3 | Active |
| US8922237B2 | Semiconductor integrated circuit with testing and repairing via | Electricity | 3 | Active |
| US9324380B2 | Stacked semiconductor apparatus and semiconductor system capable of inputting signals through various paths | Electricity | 3 | Active |
| US9959184B2 | Input/output (I/O) line test device and method for controlling the same | Physics | 3 | Active |
| US7940074B2 | Data transmission circuit and semiconductor apparatus including the same | Electricity | 2 | Active |
| US9349488B2 | Semiconductor memory apparatus | Physics | 2 | Active |
| US7915934B2 | Delay locked loop circuit and operational method thereof | Electricity | 2 | Active |
| US9396765B2 | Stacked semiconductor package | Electricity | 1 | Active |
| US8456931B2 | Data transmission device | Physics | 1 | Active |
| US8036053B2 | Semiconductor memory device capable of suppressing a coupling effect of a test-disable transmission line | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.