Integrated circuit to identify read disturb condition in memory cell
US7405964B2 · kind B2 · utility
32Cited by
4References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2006 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | Jul 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3431
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a phase change memory array is disclosed and includes identifying a read disturb condition associated with the phase change memory array, and performing a conditional refresh operation in response to the identified read disturb condition. A phase change memory is also disclosed and includes an array of phase change memory cells, and a read disturb system configured to identify a read disturb condition and perform a refresh operation on the array in response thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.