Process for fabricating chip package structure
US7407833B2 · kind B2 · utility
6Cited by
3References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 27, 2005 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Aug 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package structure comprising a carrier, a chip and an underfill layer is disclosed. The carrier has a plurality of bumps disposed thereon. The chip has an active surface. The chip is flip-chip bonded and electrically connected to the carrier through the bumps such that the active surface of the chip faces the carrier. The underfill layer is disposed on the carrier between the chip and the carrier such that a gap is maintained between the underfill layer and the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.