N+ poly on high-k dielectric for semiconductor devices
US7407850B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2005 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Mar 17, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer (308) and the polysilicon layer (310) are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region (304).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.