Registration target design for managing both reticle grid error and wafer overlay
US7408642B1 · kind B1 · utility
46Cited by
8References
37Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 17, 2006 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Jan 29, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F9/7076
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A combined overlay target and methods for its use are disclosed. The combined overlay target includes a grating-type overlay target and an image placement error target having substantially perpendicular features with spaced apart edges. The grating-type target and the image placement error target have a common centroid and are sufficiently separated that the grating-type overlay target does not interfere with measurement of image placement error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.