Minimizing effects of program disturb in a memory device
US7408810B2 · kind B2 · utility
92Cited by
12References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2006 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Nov 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected wordlines that are adjacent to the selected word line are biased at an initial Vpass. As the quantity of program/erase cycles on the memory device increases, the programming voltage required to successfully program the cells decreases incrementally. Vpass tracks the decrease of the programming voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.