Block erase for volatile memory
US7408813B2 · kind B2 · utility
7Cited by
32References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 3, 2006 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Aug 18, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a memory device to a fixed logic level. The memory cells of the block of memory cells are selected and refreshed to the fixed logic level. A sense amplifier includes a clamping circuit adapted to connect one of a digit line and an I/O line to a fixed logic level in response to an erase signal during a refresh of the selected block of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.