Simulating a floating wordline condition in a memory device, and related techniques
US7408833B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2006 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Oct 7, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and methods to exploit extra or dummy wordlines in the memory device, wherein the extra wordlines are not part of a main memory area of the memory device but, when activated, connect their attached memory cells to the bitlines of the main memory area. The extra wordlines are connected to a voltage in such a manner so as to simulate a floating wordline condition. Associated with each extra wordline is a driver circuit that connects the extra wordline to a voltage to allow it to charge up to the voltage, and subsequently disconnects the wordline from the voltage to allow it to float. While the extra wordline is floating, measurements may be made on the memory device to gather data useful for testing production memory chips for floating wordline conditions. According to another aspect, one or more extra wordlines may be activated to connect its attached memory cells to bitlines, thereby increasing the capacitance on the bitlines. This is useful during certain test mode conditions of a memory device, or on a more permanent basis to enhance the performance of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.