Stressed MOS device and method for its fabrication
US7410859B1 · kind B1 · utility
51Cited by
1References
16Claims
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Key dates
| Filing date | Nov 7, 2005 |
| Grant date | Aug 12, 2008 |
| Priority date | — |
| Expiry date | Sep 1, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
A stressed MOS device and a method for its fabrication are provided. The MOS device comprises a substrate having a surface, the substrate comprising a monocrystalline semiconductor material having a first lattice constant. A channel region is formed of the monocrystalline silicon material adjacent the surface. A stress inducing monocrystalline semiconductor material having a second lattice constant greater than the first lattice constant is grown under the channel region to exert a horizontal tensile stress on the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.