Patent · US Expired

Nonvolatile memory cell arrangement

US7411822B2 · kind B2 · utility

13Cited by

2References

19Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Michael Specht · Munich, DE
Franz Hofmann · Munich, DE
Ulrich Dorda · Wien, AT
Johannes Kretz · Birkenfeld, DE
Lars Dreeskornfeld · Dresden, DE

Key dates

Filing date	Nov 18, 2005
Grant date	Aug 12, 2008
Priority date	—
Expiry date	Nov 22, 2025

Classification

Technology area (CPC H)Electricity
CPC primaryH10D30/62
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Memory transistors are arranged in a plurality of rows and columns. A first source/drain terminal of each memory transistor of a first column is connected to an electrically conductive conductor track in a first metallization plane, and a first source/drain terminal of each memory transistor of a second column adjacent to the first column is connected to an electrically conductive conductor track in a second metallization plane.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.