Structure and method of applying localized stresses to the channels of PFET and NFET transistors for improved performance
US7414293B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2006 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | Jan 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.