Pre-decode error handling via branch correction
US7415638B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2004 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | Oct 28, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/382
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is forced to evaluate as a branch instruction. In particular, the branch instruction is evaluated as “mispredicted not taken” with a branch target address of the incorrectly pre-decoded instruction's address. This, with the invalidated cache line, causes the incorrectly pre-decoded instruction to be re-fetched from memory with a precise address. The re-fetched instruction is then correctly pre-decoded, written to the cache, and executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.