Method for producing an SOI field effect transistor
US7416927B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2004 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | Apr 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method for producing a first SOI field effect transistor with predetermined transistor properties by forming a laterally delimited layer sequence with a gate-insulating layer and a gate region on an undoped substrate, forming a spacer layer having a predetermined thickness, on at least a portion of the sidewalls of the laterally delimited layer sequence, and forming two source/drain regions having a predetermined dopant concentration profile, by introducing dopant into two surface regions of the substrate which are adjoined by the spacer layer, the layer sequence and the spacer layer forming a shading structure that prevents dopant from being introduced into a surface region of the substrate between the two source/drain regions, wherein the predetermined transistor properties of the first SOI field effect transistor are set by setting the thickness of the spacer layer and by setting the dopant concentration profile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.