Methods for fabricating a stress enhanced MOS circuit
US7416931B2 · kind B2 · utility
2Cited by
3References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 22, 2006 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | Oct 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
Methods are provided for fabricating a stress enhanced MOS circuit. One method comprises the steps of depositing a stressed material overlying a semiconductor substrate and patterning the stressed material to form a stressed dummy gate electrode overlying a channel region in the semiconductor substrate so that the stressed dummy gate induces a stress in the channel region. Regions of the semiconductor substrate adjacent the channel are processed to maintain the stress to the channel region and the stressed dummy gate electrode is replaced with a permanent gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.