Gen Pei
9Patents
6h-index
12Co-inventors
52Inventor score
Filing activity: Mar 16, 2006 → Mar 21, 2011
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8012820B2 | Ultra-thin SOI CMOS with raised epitaxial source and drain and embedded SiGe PFET extension | Electricity | 37 | Active |
| US7439120B2 | Method for fabricating stress enhanced MOS circuits | Electricity | 24 | Active |
| US7816767B2 | Negative differential resistance diode and SRAM utilizing such device | Electricity | 18 | Active |
| US7508050B1 | Negative differential resistance diode and SRAM utilizing such device | Electricity | 17 | Active |
| US8400854B2 | Identifying at-risk data in non-volatile storage | Physics | 7 | Active |
| US7442601B2 | Stress enhanced CMOS circuits and methods for their fabrication | Electricity | 7 | Active |
| US7943999B2 | Stress enhanced MOS circuits | Electricity | 2 | Active |
| US7416931B2 | Methods for fabricating a stress enhanced MOS circuit | Electricity | 2 | Active |
| US9373548B2 | CMOS circuit having a tensile stress layer overlying an NMOS transistor and overlapping a portion of compressive stress layer | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.