Methods for fabricating flash memory devices
US7416940B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2006 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | Oct 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/30
Abstract
Methods for fabricating a flash memory device are provided. A method comprises forming a plurality of gate stacks overlying a substrate. Each gate stack comprises a charge trapping layer and a control gate. The control gate is a first distance from the substrate. Adjacent gate stacks are a second distance apart. A cell spacer material layer is deposited and is etched to form a spacer about sidewalls of each gate stack. A source/drain impurity doped region is formed adjacent a first gate stack and a last gate stack. The first distance and the second distance are such that, when a voltage is applied to a gate stack during a READ operation, a fringing field is created between the control gate of the gate stack and the substrate and is sufficient to invert a portion of the substrate between the gate stack and an adjacent gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.