IC chip package with cover
US7417327B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2005 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | Apr 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16195
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An IC (integrated circuit) chip package includes a substrate (2), a chip (3), a plurality of bonding wires (32), and a cover (5). The substrate has a top surface, a bottom surface, a receiving chamber (23) defined therein, a plurality of solder pads (24) arranged around the top surface and the bottom surface, and a plurality of vias (25) having conductive material electrically connecting the top solder pads with the bottom solder pads defined therein. The chip is mounted in the receiving chamber, and has a plurality of chip solder pads arranged around a top surface thereof. The bonding wires respectively electrically connect the top solder pads of the substrate with the chip solder pads. The cover is fastened to the top surface of the substrate to cover the opening, and has a smaller profile than that of the substrate, thereby not cover a peripheral area of the top surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.