Method for reading a single-poly single-transistor non-volatile memory cell
US7417897B2 · kind B2 · utility
7Cited by
7References
14Claims
0Family size
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Key dates
| Filing date | Jan 23, 2007 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | Apr 20, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a single-poly, single-transistor (1-T) non-volatile memory (NVM) cell. The NVM cell includes a gate on a P substrate, a gate dielectric layer, an N drain region and an N source region. N channel is defined between the N drain region and N source region. The NVM cell is programmed by breaking down the gate dielectric layer. To read the NVM cell, a positive voltage is provided to N drain region, a positive voltage is provided to the gate, and grounding the N source region and the P substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.