Method of making a semiconductor chip assembly with a metal containment wall and a solder terminal
US7419851B2 · kind B2 · utility
7Cited by
155References
200Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2005 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Jan 26, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor chip assembly includes providing a metal base, a routing line, a metal containment wall and a solder layer in which the metal containment wall includes a cavity and the solder terminal contacts the metal containment wall in the cavity, mechanically attaching a semiconductor chip to the routing line, forming a connection joint that electrically connects the routing line and the pad, etching the metal base to reduce contact area between the metal base and the routing line and between the metal base and the metal containment wall, and providing a solder terminal that includes the solder layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.