Method to remove an oxide seam along gate stack edge, when nitride space formation begins with an oxide liner surrounding gate stack
US7420240B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 25, 2003 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Jul 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
An exposed top end of a vertical oxide spacer is removed, and a nitride layer is deposited in an amount sufficient to replace the removed portion prior to exposing a memory device to a self align contact etch process. The nitride layer may be used to prevent a short circuit through the oxide spacer. The present invention also provides memory devices that have a gate stack, a vertical spacer adjacent to the gate stack, in which the vertical spacer has a lower portion comprising an oxide and an upper portion comprising a nitride, and a continuous nitride layer overlaying the vertical spacer and the gate stack. The present invention further provides methods of fabricating the above devices, and processor systems which include the devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.