Patent · US Expired

Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals

US7420430B2 · kind B2 · utility

0Cited by

6References

19Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Claudio Andreotti · Munich, DE
Edoardo Prete · Birkenfeld, DE
Anthony Sanders · Birkenfeld, DE

Key dates

Filing date	Aug 1, 2005
Grant date	Sep 2, 2008
Priority date	—
Expiry date	Aug 1, 2025

Classification

Technology area (CPC H)Electricity
CPC primaryH04L7/0025
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals.A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock signals (s, c) that have a predetermined phase relationship to one another, are weighted with respective weighting factors (A, 1-A), and in which the weighted input clock signals (s′, c′) are added in order to generate a summated clock signal (i). The summated clock signal (i) is integrated in an integrator (8) and optionally amplified in order to generate the output clock signal (o). An output clock signal (o) with an adjustable phase relation can be generated with such a method and such an arrangement, in which the requirements placed on the input clock signals are less stringent.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.