Method of programming a three-terminal non-volatile memory element using source-drain bias
US7420842B1 · kind B1 · utility
4Cited by
11References
10Claims
0Family size
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Key dates
| Filing date | Aug 24, 2005 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Dec 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage transistor is programmed as a non-volatile memory element by biasing the source and drain while a programming voltage is applied to the gate. The substrate is held at a different potential than the source/drain to insure that the greatest difference in voltage during the programming step occurs between the channel region and the gate, rather than the gate and the source/drain. The programming voltage heats the channel region to form a non-volatile low-resistance connection between the source and drain, which is read to determine the programmed state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.