Method, system, and circuit for operating a non-volatile memory array
US7420848B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Jan 9, 2006 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Jan 24, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3436
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.