Patent · US Expired

Integrated circuit with re-route layer and stacked die assembly

US7422930B2 · kind B2 · utility

14Cited by

15References

60Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Jochen Thomas · Munich, DE
Peter Weitz · Sauerlach, DE
Jurgen Grafe · Dresden, DE
Harry Hedler · Germering, DE
Jens Pohl · San Luis Obispo, US

Key dates

Filing date	Mar 2, 2004
Grant date	Sep 9, 2008
Priority date	—
Expiry date	Jan 17, 2025

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/30107
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the bond pads of the first die to contacts on the substrate. A second die is placed on the first die, and wire leads electrically couple the bond pads of the second die to contacts on the substrate. Preferably, a spacer is placed between the first die and the second die. Additional dies may be stacked on the second die.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.