Multi-step process for patterning a metal gate electrode
US7422969B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Sep 26, 2007 |
| Grant date | Sep 9, 2008 |
| Priority date | — |
| Expiry date | Sep 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.