Strain-silicon CMOS using etch-stop layer and method of manufacture
US7423283B1 · kind B1 · utility
9Cited by
22References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 7, 2005 |
| Grant date | Sep 9, 2008 |
| Priority date | — |
| Expiry date | Jun 7, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Recesses are formed in the drain and source regions of an MOS transistor. An ohmic contact layer is formed in the recesses, and a stressed silicon-nitride layer is formed over the ohmic contact layer. The recesses allow the stressed silicon nitride layer to provide strain in the plane of the channel region. In a particular embodiment, a tensile silicon nitride layer is formed over recesses of an NMOS transistor in a CMOS cell, and a compressive silicon nitride layer is formed over recesses of a PMOS transistor in the CMOS cell. In a particular embodiment the stressed silicon nitride layer(s) is a chemical etch stop layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.