Single-gate non-volatile memory and operation method thereof
US7423903B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2006 |
| Grant date | Sep 9, 2008 |
| Priority date | — |
| Expiry date | Dec 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.