SONOS memory array with improved read disturb characteristic
US7423912B2 · kind B2 · utility
9Cited by
7References
8Claims
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Key dates
| Filing date | Sep 19, 2006 |
| Grant date | Sep 9, 2008 |
| Priority date | — |
| Expiry date | Sep 19, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A PMOS non-volatile memory array using SONOS transistors having program and erase threshold voltages for representing digital logic states of zero and one and selected to optimize read disturb characteristics. The threshold voltages are linearly convergent and separated by at least 0.5 volts for a charge retention time of at least 10 years, with the threshold voltages defining a window wherein a read voltage for selected memory transistors can be held flat and not intersect the threshold voltages. The lower threshold is selected to be at a zero charge state for one of the two logic levels of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.