Clocking methodology for at-speed testing of scan circuits with synchronous clocks
US7424656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2005 |
| Grant date | Sep 9, 2008 |
| Priority date | — |
| Expiry date | Jan 7, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31858
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A clocking method for at-speed scan testing for delay defects in cross-domain paths of interacting synchronous clock domains in a scan circuit, each path originating from a source memory element in one of the domains and terminating at a destination memory element in another of the domains and comprises selectively aligning either a capture edge or a launch edge of the clock of each domain with a corresponding edge of at least one other domain of the interacting synchronous clock domains to determine the cross-domain paths to be tested between a source domain and a destination domain; clocking memory elements in each domain at respective domain clock rates to launch signal transitions from source memory elements in source domains; and for each pair of interacting clock domains under test, capturing, in the destination domain, circuit responses to signal transitions launched along paths originating from the source domain and selectively disabling capturing, in the source domain, of circuit responses to signal transitions launched along paths originating from the destination domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.