Semiconductor structure implementing sacrificial material and methods for making and implementing the same
US7425501B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2005 |
| Grant date | Sep 16, 2008 |
| Priority date | — |
| Expiry date | Oct 4, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a semiconductor device is provided. The method includes forming transistor structures on a substrate and forming interconnect metallization structures in a plurality of levels through depositing a sacrificial layer. A dual damascene process is performed to etch trenches and vias, and filling and planarizing the trenches and vias. The sacrificial layer is etched throughout the plurality of levels of the interconnect metallization structures, thus leaving a voided interconnect metallization structure. The voided interconnect metallization structure is filled with low K dielectric material, thus defining a low K dielectric interconnect metallization structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.