Nonvolatile semiconductor memory
US7425739B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2005 |
| Grant date | Sep 16, 2008 |
| Priority date | — |
| Expiry date | Aug 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.