Error checking parity and syndrome of a block of data with relocated parity bits
US7426678B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2004 |
| Grant date | Sep 16, 2008 |
| Priority date | — |
| Expiry date | Jul 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/45
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.