Method of forming a CMOS structure having gate insulation films of different thicknesses
US7427791B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2005 |
| Grant date | Sep 23, 2008 |
| Priority date | — |
| Expiry date | Jul 2, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/936
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.