Phase detector and method providing rapid locking of delay-lock loops
US7428284B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2005 |
| Grant date | Sep 23, 2008 |
| Priority date | — |
| Expiry date | Oct 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay-lock loop includes a dual mode phase detector. The dual mode phase detector includes a single edge phase detector that generates output signals indicative of the phase relationship between the rising edge of a reference signal and the rising edge of a feedback signal generated by the delay-lock loop. The dual mode phase detector also includes a dual edge phase detector that generates output signals indicative of the phase relationship between both the rising edge of a reference signal and the rising edge of the feedback signal and the falling edge of a reference signal and the falling edge of the feedback signal. A lock detector controls a switch so that it couples the output signals from the single edge phase detector to a delay line when the loop is locked, and it otherwise couples the output signals from the dual edge phase detector to the delay line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.