Arithmetic unit for addition or subtraction with preliminary saturation detection
US7428567B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2004 |
| Grant date | Sep 23, 2008 |
| Priority date | — |
| Expiry date | Jan 27, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49921
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, such as respective less significant and more significant portions. The arithmetic unit comprises first arithmetic circuitry, second arithmetic circuitry, selection circuitry and saturation circuitry. The first arithmetic circuitry, which may comprise a carry-propagate adder, processes the first portions of the input operands to generate at least a temporary sum and a carry output. The second arithmetic circuitry, which may comprise a dual adder and a preliminary saturation detector, processes the second portions of the input operands to generate one or more temporary sums and a number of saturation flags. The selection circuitry is configured to select one or more of the outputs of the second arithmetic circuitry based on the carry output of the first arithmetic circuitry. The saturation circuitry has inputs coupled to corresponding outputs of the first arithmetic circuitry and the selection circuitry, and is configured to generate a result of the arithmetic operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.