Method of forming silicide gate with interlayer
US7429526B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2006 |
| Grant date | Sep 30, 2008 |
| Priority date | — |
| Expiry date | Aug 9, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/668
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field-effect transistor (“FET”) or similar device has a fully silicided (“FUSI”) gate electrode. The gate electrode has a gate interface silicide portion between the gate dielectric and a bulk gate silicide portion. The gate interface silicide is formed by depositing a gate electrode interface layer having silicide retardation species underneath the metal/silicon layers used to form the gate silicide. The gate electrode interface layer retards silicide formation at the gate dielectric/gate electrode interface when the bulk gate silicide is formed, and the gate interface silicide is then formed at a higher temperature or longer heat cycle time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.