Multi-bit flash memory device having improved program rate
US7433228B2 · kind B2 · utility
4Cited by
31References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2005 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Feb 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.