Lithographically optimized placement tool
US7434188B1 · kind B1 · utility
2Cited by
2References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2006 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Mar 16, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and a method are disclosed for integrating the results of lithographic simulation into the physical synthesis process. The effects of lithographic variation are considered when selecting a cell from among a group of cells having equivalent function. Circuit design elements are placed and routed with consideration of the effects of lithographic variation on robustness, timing performance, and leakage current. Cells may be simulated under a variety of conditions and environments and the simulation results stored in a library for efficient lithographically optimized placements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.