Trilayer resist scheme for gate etching applications
US7435671B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2006 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Dec 1, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28123
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material. The bottom organic layer of the TLR comprises any organic layer such as, for example, a Near Frictionless Carbon (NFC), a diamond-like carbon, a thermosetting polyarylene ether.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.