Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel
US7435988B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2005 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Sep 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A semiconductor device may include a substrate and at least one MOSFET adjacent the substrate including a superlattice. The superlattice may include a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers. Each group of layers of the superlattice may comprise a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The MOSFET may further include source, drain, and gate regions defining a channel through at least a portion of the semiconductor cap layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.