Chip package without core and stacked chip package structure thereof
US7436074B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 13, 2005 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | May 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package without a core, including a patterned circuit layer, a chip, a solder mask, a molding compound and multiple outer terminals, is provided. The patterned circuit layer has a first surface and a second surface opposite to each other. The chip disposed on the first surface is electrically connected to the patterned circuit layer. The solder mask disposed on the second surface has a plurality of first openings by which part of the patterned circuit layer is exposed. The molding compound with a plurality of through holes cover the pattern circuit layer and fix the chip onto the patterned circuit layer. Each outer terminal disposed in the through hole is electrically connected to the patterned circuit layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.