Method for fabricating stress enhanced MOS circuits
US7439120B2 · kind B2 · utility
24Cited by
3References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 11, 2006 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Oct 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stress enhanced MOS circuit and methods for its fabrication are provided. The stress enhanced MOS circuit comprises a semiconductor substrate and a gate insulator overlying the semiconductor substrate. A gate electrode overlies the gate insulator; the gate electrode has side walls and comprising a layer of polycrystalline silicon having a first thickness in contact with the gate insulator and a layer of electrically conductive stressed material having a second thickness greater than the first thickness overlying the layer of polycrystalline silicon. A stress liner overlies the side walls of the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.