Methods to fabricate MOSFET devices using a selective deposition process
US7439142B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2006 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Mar 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method for forming a silicon-based material on a substrate having dielectric materials and source/drain regions thereon within a process chamber is provided which includes exposing the substrate to a first process gas comprising silane, methylsilane, a first etchant, and hydrogen gas to deposit a first silicon-containing layer thereon. The first silicon-containing layer may be selectively deposited on the source/drain regions of the substrate while the first silicon-containing layer may be etched away on the surface of the dielectric materials of the substrate. Subsequently, the process further provides exposing the substrate to a second process gas comprising dichlorosilane and a second etchant to deposit a second silicon-containing layer selectively over the surface of the first silicon-containing layer on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.