Isolation trenches for memory devices
US7439157B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2005 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Aug 15, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric layer on at least the first dielectric layer, the second dielectric layer containing a different dielectric material than the first dielectric layer; depositing a third dielectric layer to fill the trench; removing an upper portion of the third dielectric layer from the trench and leaving a lower portion covering a portion of the second dielectric layer; oxidizing the lower portion of the third dielectric layer after removing the upper portion; removing an exposed portion of the second dielectric layer from the trench, thereby exposing a portion of the first dielectric layer; and forming a fourth dielectric layer in the trench covering the exposed portion of the first dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.