Method of fabricating tensile strained layers and compressive strain layers for a CMOS device

US7439165B2 · kind B2 · utility

Assignee

• AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH · SG

Inventors

• Patrick Guo-Qiang Lo · Singapore, SG
• Lakshmi Kanta Bera · Singapore, SG
• Wei-Yip Loh · Hsinchu, TW
• Balakumar Subramanian · Singapore, SG
• Narayanan Balasubramanian · Singapore, SG

Key dates

• Filing date: Apr 6, 2005
• Grant date: Oct 21, 2008
• Expiry date: Jul 31, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0188

Abstract

A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and activation procedures, the fabrication sequences used to obtain the strained silicon layers is initiated. A semiconductor alloy layer is deposited followed by an oxidation procedure used to segregate a germanium component from the overlying semiconductor alloy layer into an underlying single crystalline silicon body. The level of germanium segregated into the underlying single crystalline silicon body determines the level of strain, which is in tensile state of a subsequently selectively grown silicon layer. A second embodiment of this invention features the thinning of a portion of the semiconductor alloy layer prior to the oxidation procedure allowing a lower level of germanium to be segregated into a first underlying portion of the underlying single crystalline silicon body, while during the same oxidation procedure a second portion of the underlying single crystalline silicon body receives a higher level of germanium s…