Two-port SRAM having improved write operation
US7440313B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2006 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Nov 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two-port SRAM memory cell includes a pair of cross-coupled inverters coupled to storage nodes. An access transistor is coupled between each storage node and a write bit line and controlled by a write word line. The write word line is also coupled to a power supply terminal of the pair of cross-coupled inverters. During a write operation, the write word line is asserted. A voltage at the power supply terminal of the cross-coupled inverters follows the write word line voltage, thus making it easier for the stored logic state at the storage nodes to change, if necessary. At the end of the write operation, the write word line is de-asserted, allowing the cross-coupled inverters to function normally and hold the logic state of the storage node. Coupling the power supply node of the cross-coupled inverters allows faster write operations without harming cell stability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.